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> In the end, programs will want probably to stay conservative and will implement only the core ISA This is probably not the case. The core ISA doesn't include
by mort96 1y ago
> In the end, programs will want probably to stay conservative and will implement only the core ISA
This is probably not the case. The core ISA doesn't include floating point, it doesn't include integer multiply or divide, it doesn't include atomic and fence instructions.
What has happened is that most compilers and programs for "normal desktop/laptop/server/phone class systems" all have some baseline set of extensions. Today, this is more or less what we call the "G" extension collection (which is short-hand for IMAFD_Zicsr_Zifencei). Though what we consider "baseline" in "normal systems" will obviously evolve over time (just like how SSE is considered a part of "baseline amd64" these days but was once a new and exotic extension).
Then lower power use cases like MCUs will have fewer instructions. There will be lots of MCUs without stuff like hardware floating point support that won't run binaries compiled for the G extension collection. In MCU use cases, you typically know at the time of compiling exactly what MCU your code will be running on, so passing the right flags to the compiler to make sure it generates only the supported instructions is not an issue.
And then HPC use cases will probably assume more exotic extensions.
And normal "desktop/phone/laptop/server" style use cases will have runtime detection of things like vector instructions in some situations, just like in aarch64/amd64.
- panick21_ 1y agoIts not known as "G". The standard that is target by the software ecosystem is RVA20, RVA22, RVA23. https://riscv.org/ecosystem-news/2025/04/risc-v-rva23-a-major-milestone/ https://riscv.org/ecosystem-news/2025/04/risc-v-rva23-a-majo...
- mort96 1y agoThanks, seems I'm out of date (or just wrong). G is indeed IMAFD_Zicsr_Zifencei and I've always viewed it as a "reasonable baseline for most normal code", I wasn't up to date on the RVA/B/C stuff.
- panick21_ 1y agoGenerally RV64GC was the original target and was renamed and is basically RVA20.
- int_19h 1y agoWas there ever a time when SSE was not a part of baseline amd64? Just going off the dates, SSE showed up in Pentium 3, and if I remember correctly AMD picked it up in 32-bit Athlons already.
- mort96 1y agoI think you're right. I should've said x86 (or maybe IA-32?), not amd64.
- dzaima 1y agogcc, via -m32, still defaults to no SSE, i.e. pre-1999, i.e. ≥26 years and counting for increasing default. clang, as far back as Compiler Explorer goes (i.e. clang 3.0.0, i.e. 2011), always assumes SSE for -m32; presumably because there's nothing to be backwards-compatible to, unlike gcc. Doesn't look particularly good for "default will just change at some point", though we can hope.
- sylware 1y agoWhat?? Ofc, if your program uses floating point calculations you will want to use the hardware machine instructions for that. Here, we were talking about about all those machine instructions which do not bring much more on top of the core ISA. Those would be implemented using fusion, appropriate for R(educed)ISC silicon. The trade-off is code density, and code density on modern silicon, probably in very specific niches, but there, program machine instructions would be generated (BTW, probably written instead of generated for those niches...) with those very specific niches in mind. And RISC-V hardware implementations, with proper publishing of most common, and pertinent, machine instruction fusion patterns, will be able to "improve" step by step, targetting what they actually run and what would make real difference. Sure, this will require a bit of coordination to agree on machine instruction fusion patterns.
- mort96 1y agoYou said "programs will want probably to stay conservative and will implement only the core ISA". I'm saying that the core ISA is very very limited and most programs will want to use more than the core ISA.
- sylware 1y agoWhat??? Re-read my post, please. The problem is those machine instructions not bringing much more than the core ISA which do not require an ISA extension.