3 ms·
Not necessarily lower density. On ARM you would often need cmp and csel, which are two instructions, eight bytes. RISC-V has cmp-and-branch in a single instruc
by Findecanor 1y ago
Not necessarily lower density. On ARM you would often need cmp and csel, which are two instructions, eight bytes.
RISC-V has cmp-and-branch in a single instruction, which with c.mv normally makes six bytes. If the cmp-and-branch instruction tests one of x8..x15 against zero then that could also be a compressed instruction: making four bytes in total.
- astrange 1y agoARMv8.7 added some new instructions for int min/max to replace cmp+csel. (I'm surprised it took them so long to add popcnt.) https://www.corsix.org/content/arm-cssc https://www.corsix.org/content/arm-cssc
- sylware 1y agoCompressed instruction only matter for niche (and even in such niche, nowadays, I guess it is very probably very questionable), here you would not use compressed instructions, just the right instruction pattern for fusion, like div/rem.