> - only do aligned memory accesses TriCore 16/32bit reads/writes are like that. So doing something like uint8_t array8[] = {bytes here}; uint32_t i = *(array

> - only do aligned memory accesses TriCore 16/32bit reads/writes are like that. So doing something like uint8_t array8[] = {bytes here}; uint32_t i = *(array8 + 1); will crash your processor and force reset it, because you just tried to make a read on odd address (assuming that array is aligned on even address) > - expose your pipeline details in the ISA Again TriCore and division - DVINIT then repeatedly poke DVSTEP and then call DVADJ to store result into a register... Or SH2A architecture where you are always grouping instructions by 2, processed in parallel I suppose?