3 ms·
No, the performance problem I'm referring to is the Load Hit Store problem, where the pipeline is constantly stalled (in-order execution) waiting for the CPU to
by hythloday 14y ago
No, the performance problem I'm referring to is the Load Hit Store problem, where the pipeline is constantly stalled (in-order execution) waiting for the CPU to write to L1 cache.
- loup-vaillant 14y agoThis is more by chance than anything, but I think my correction addresses precisely that: the point is not to hoist the increment out of the loop. The point is to hoist the member access. That way, you end up with only one write to memory, instead of a write and a read. (There is another member access in the condition of the loop, but I guess the compiler can optimize it.) I explained that here: http://news.ycombinator.com/item?id=4540107 http://news.ycombinator.com/item?id=4540107 I did not get the Load Hit Store problem, but I did sense there was a problem with the repeated read access to memory. By the way, it looks like your problem is a bit more subtle than the textbook Load Hit Store: you don't read the location you just wrote to. I guess the write access dirties more than one word (at least a cache line, maybe more).