3 ms·

This dismisses the entire field of modern high-speed digital design. At GHz frequencies, the PCB isn't a passive substrate; it's an active RF component. Managi

This dismisses the entire field of modern high-speed digital design. At GHz frequencies, the PCB isn't a passive substrate; it's an active RF component. Managing signal integrity, controlling impedance, and mitigating EMI in a dense layout is a monumental engineering challenge, not a solved problem from the "1930s radio" era. The AMD comparison is backward. AMD provides public datasheets and reference designs. This schematic is valuable precisely because Apple's silicon is a black box. It's the only public blueprint for a successful, validated implementation. The chip and board are a co-designed system. A brilliant SoC is useless without the board-level engineering to power it cleanly and cool it within a tiny physical envelope. That system integration is the R&D.

throwaway31131 1y ago
But all that information is in the engineering files that are neither the schematic or the layout. You might guess some information from the layout, but on some crazy HDI PCB like the iPhone uses, you'll be missing most of the information needed to take advantage of it. Any signal that uses passive termination, and would therefore show up in the schematic, is basically a tacit admission that this line needs something, but basically anything remotely close to 50Ω will do. Which is something you could've gathered by inspection of the final product.
cogman10 1y ago
> This dismisses the entire field of modern high-speed digital design. No it doesn't. That entire field operates primarily within the ASICs, not the PCB. > At GHz frequencies, the PCB isn't a passive substrate; Yes, it actually is. There is some noise and cross talk that's emitted from the signals but it's minimal and easily blocked. Very simple rules, like minimum trace distances, solve pretty much any problem that comes up from the frequency of the signals. But further, those problems are peanuts compared to dealing with the exact same problem within the ASIC. Very simple rules are needed for the PCB. > mitigating EMI in a dense layout is a monumental engineering challenge, not a solved problem from the "1930s radio" era. You are vastly overblowing how big an issue or problem this is. The voltages and current on the lines are minimized to cut back on EMF and power consumption. Those are dictated by the chip design, not the PCB setup. > A brilliant SoC is useless without the board-level engineering to power it cleanly and cool it within a tiny physical envelope. That system integration is the R&D. There is some R&D that goes into the board, for sure. However you are completely overblowing how hard or costly it is for apple or others to develop.
- varispeed 1y ago
  This demonstrates a profound misunderstanding of the physics of high-speed electronics. High-speed design doesn't stop at the ASIC boundary; that's often where the hardest part begins. The entire field of SerDes engineering exists to solve the "trivial" problem of getting multi-gigabit signals off the chip and across the board to RAM or a port without dissolving into noise. It's a system-level challenge. At GHz frequencies, a PCB trace is not a passive wire; it is a transmission line. The idea that "simple rules" for trace distance solve this is fundamentally incorrect. Real-world design requires complex electromagnetic simulation to control impedance, manage signal reflections, and design via structures that don't destroy the signal. This is why Signal Integrity (SI) is a dedicated engineering discipline. EMI is caused by the rate of change of current (dI/dt), not just the voltage level. Modern chips have incredibly fast signal rise/fall times to achieve high performance, which creates massive high-frequency energy that radiates easily. Passing FCC/CE certification is a famously difficult, multi-million-dollar R&D effort, not a trivial detail.
  - cogman10 1y ago
    I don't think you realize it, but this completely refutes your initial point. That the schematics are valuable and something that someone could simply copy for their own board designs. You can't hold both positions that there is a bunch of system dependent physics involved AND that someone can simply copy those design elements and pass CE/FCC licensing. And no, I don't misunderstand it. > The entire field of SerDes engineering exists to solve the "trivial" problem of getting multi-gigabit signals off the chip and across the board to RAM or a port without dissolving into noise. It's a system-level challenge. Right, and most of the problem is inside the specification of the signal. It has (almost) nothing to do with the actual PCB design beyond talking about the voltages and acceptable trace lengths. You are forgetting exactly what the initial discussion is about, whether or not the schematics are valuable to other hardware manufacturers. > Real-world design requires complex electromagnetic simulation to control impedance, manage signal reflections, and design via structures that don't destroy the signal. This is why Signal Integrity (SI) is a dedicated engineering discipline. Simulations that are completely missing from the schematics, correct? You don't even get to glean what those simulations would be and importantly minor changes could by your logic completely ruin a design. Correct? This is the weakness of your argument. Yes, these things matter. But you are frankly overblowing how complex or hard they are to create. Everyone is doing them and it's not a huge cost to the actual hardware manufacturing. > Passing FCC/CE certification is a famously difficult, multi-million-dollar R&D effort, not a trivial detail. There are hobbiests that have managed to pass the FCC/CE certification with their own custom PCBs. Look, I admit that it's something harder to do with high speed signals. However, it's not a "multi-million-dolar R&D effort" That is, unless you are wrapping the VP of engineering's salary into that calculation. The biggest problem you actually face as a hardware company is that if there is an issue you have to redesign and resubmit to the FCC/CE which takes a time. Online, I'm finding people saying that 4 or 5 respins is common. Apple spending more money here would be entirely around avoiding that respin. Buying the same testing equipment and shoring up the testing procedures to make sure they get the certification the first or second time rather than spending a bunch of time needing to retry. Which, I can't stress enough, is not something that comes out of the schematics. You as a competitor don't get any real information about the testing that was done and you certainly get no information about what the high speed communications between chips looks like (though that is entirely going away).

throwaway31131 1y ago

But all that information is in the engineering files that are neither the schematic or the layout. You might guess some information from the layout, but on some crazy HDI PCB like the iPhone uses, you'll be missing most of the information needed to take advantage of it. Any signal that uses passive termination, and would therefore show up in the schematic, is basically a tacit admission that this line needs something, but basically anything remotely close to 50Ω will do. Which is something you could've gathered by inspection of the final product.

cogman10 1y ago

> This dismisses the entire field of modern high-speed digital design. No it doesn't. That entire field operates primarily within the ASICs, not the PCB. > At GHz frequencies, the PCB isn't a passive substrate; Yes, it actually is. There is some noise and cross talk that's emitted from the signals but it's minimal and easily blocked. Very simple rules, like minimum trace distances, solve pretty much any problem that comes up from the frequency of the signals. But further, those problems are peanuts compared to dealing with the exact same problem within the ASIC. Very simple rules are needed for the PCB. > mitigating EMI in a dense layout is a monumental engineering challenge, not a solved problem from the "1930s radio" era. You are vastly overblowing how big an issue or problem this is. The voltages and current on the lines are minimized to cut back on EMF and power consumption. Those are dictated by the chip design, not the PCB setup. > A brilliant SoC is useless without the board-level engineering to power it cleanly and cool it within a tiny physical envelope. That system integration is the R&D. There is some R&D that goes into the board, for sure. However you are completely overblowing how hard or costly it is for apple or others to develop.

varispeed 1y ago
This demonstrates a profound misunderstanding of the physics of high-speed electronics. High-speed design doesn't stop at the ASIC boundary; that's often where the hardest part begins. The entire field of SerDes engineering exists to solve the "trivial" problem of getting multi-gigabit signals off the chip and across the board to RAM or a port without dissolving into noise. It's a system-level challenge. At GHz frequencies, a PCB trace is not a passive wire; it is a transmission line. The idea that "simple rules" for trace distance solve this is fundamentally incorrect. Real-world design requires complex electromagnetic simulation to control impedance, manage signal reflections, and design via structures that don't destroy the signal. This is why Signal Integrity (SI) is a dedicated engineering discipline. EMI is caused by the rate of change of current (dI/dt), not just the voltage level. Modern chips have incredibly fast signal rise/fall times to achieve high performance, which creates massive high-frequency energy that radiates easily. Passing FCC/CE certification is a famously difficult, multi-million-dollar R&D effort, not a trivial detail.
- cogman10 1y ago
  I don't think you realize it, but this completely refutes your initial point. That the schematics are valuable and something that someone could simply copy for their own board designs. You can't hold both positions that there is a bunch of system dependent physics involved AND that someone can simply copy those design elements and pass CE/FCC licensing. And no, I don't misunderstand it. > The entire field of SerDes engineering exists to solve the "trivial" problem of getting multi-gigabit signals off the chip and across the board to RAM or a port without dissolving into noise. It's a system-level challenge. Right, and most of the problem is inside the specification of the signal. It has (almost) nothing to do with the actual PCB design beyond talking about the voltages and acceptable trace lengths. You are forgetting exactly what the initial discussion is about, whether or not the schematics are valuable to other hardware manufacturers. > Real-world design requires complex electromagnetic simulation to control impedance, manage signal reflections, and design via structures that don't destroy the signal. This is why Signal Integrity (SI) is a dedicated engineering discipline. Simulations that are completely missing from the schematics, correct? You don't even get to glean what those simulations would be and importantly minor changes could by your logic completely ruin a design. Correct? This is the weakness of your argument. Yes, these things matter. But you are frankly overblowing how complex or hard they are to create. Everyone is doing them and it's not a huge cost to the actual hardware manufacturing. > Passing FCC/CE certification is a famously difficult, multi-million-dollar R&D effort, not a trivial detail. There are hobbiests that have managed to pass the FCC/CE certification with their own custom PCBs. Look, I admit that it's something harder to do with high speed signals. However, it's not a "multi-million-dolar R&D effort" That is, unless you are wrapping the VP of engineering's salary into that calculation. The biggest problem you actually face as a hardware company is that if there is an issue you have to redesign and resubmit to the FCC/CE which takes a time. Online, I'm finding people saying that 4 or 5 respins is common. Apple spending more money here would be entirely around avoiding that respin. Buying the same testing equipment and shoring up the testing procedures to make sure they get the certification the first or second time rather than spending a bunch of time needing to retry. Which, I can't stress enough, is not something that comes out of the schematics. You as a competitor don't get any real information about the testing that was done and you certainly get no information about what the high speed communications between chips looks like (though that is entirely going away).