For the curious: the process of discovering the logic and route timings for an FPGA device is to use ring oscillators (three series inverters) and compare count

For the curious: the process of discovering the logic and route timings for an FPGA device is to use ring oscillators (three series inverters) and compare counters against a known clock. Place the inverters all over to test every LUT, and use every routing path to test each path's timing.