CHERI: Capability Hardware Enhanced RISC Instructions: https://en.wikipedia.org/wiki/Capability_Hardware_Enhanced_RISC_Instructions https://en.wikipedia.org/wi

CHERI: Capability Hardware Enhanced RISC Instructions: https://en.wikipedia.org/wiki/Capability_Hardware_Enhanced_RISC_Instructions https://en.wikipedia.org/wiki/Capability_Hardware_Enhanced_R... Is the (page-level) NX bit almost capability based addressing? Capability-based addressing: https://en.wikipedia.org/wiki/Capability-based_addressing https://en.wikipedia.org/wiki/Capability-based_addressing