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Adding Capability Hardware Enhanced RISC Instructions (CHERI) to Linux
- westurner 1y agoCHERI: Capability Hardware Enhanced RISC Instructions: https://en.wikipedia.org/wiki/Capability_Hardware_Enhanced_RISC_Instructions https://en.wikipedia.org/wiki/Capability_Hardware_Enhanced_R... Is the (page-level) NX bit almost capability based addressing? Capability-based addressing: https://en.wikipedia.org/wiki/Capability-based_addressing https://en.wikipedia.org/wiki/Capability-based_addressing