Theoretically the vector extensions in a RISC-V could be scaled considerably, it seems to me, especially when combined with the extension proposed here: https:/

Theoretically the vector extensions in a RISC-V could be scaled considerably, it seems to me, especially when combined with the extension proposed here: https://github.com/spacemit-com/riscv-ime-extension-spec https://github.com/spacemit-com/riscv-ime-extension-spec That said, the actual processor cores in this SBC seem to max out at 256 bit registers, which does not seem to be a lot.