Not sure where you're getting L1 from. The folly comment doesn't mention it. FWIW, IA-32 SDM Vol 3A, section 10.10.6.7 still explicitly recommends 128-byte al

Not sure where you're getting L1 from. The folly comment doesn't mention it. FWIW, IA-32 SDM Vol 3A, section 10.10.6.7 still explicitly recommends 128-byte alignment for locks on NetBurst uarch (~Pentium 4) processors. > 10.10.6.7 Place Locks and Semaphores in Aligned, 128-Byte Blocks of Memory > When software uses locks or semaphores to synchronize processes, threads, or other code sections; Intel recommends that only one lock or semaphore be present within a cache line (or 128 byte sector, if 128-byte sector is supported). In processors based on Intel NetBurst microarchitecture (which support 128-byte sector consisting of two cache lines), following this recommendation means that each lock or semaphore should be contained in a 128-byte block of memory that begins on a 128-byte boundary. The practice minimizes the bus traffic required to service locks. There is also an interesting table of cache line and "sector" sizes in Table 13-1 (it's all 64-byte cache lines in newer Intel CPUs).