> 768KB I & D cache per core PA-RISC has mostly always had large L1 caches ( that used to be off-chip), and usually no L2 cache. I know this bit of trivia,

> 768KB I & D cache per core PA-RISC has mostly always had large L1 caches ( that used to be off-chip), and usually no L2 cache. I know this bit of trivia, but I don't know the technical reasons/trade-offs for it.