3 ms·
Trigger Crossbar
- baq 1y agoSoldered an ESP32 together with a couple I2C sensors the other week. Didn’t work. Read post, jaw hit floor, maybe I’ll revisit the project soon. Amazing.
- frainfreeze 1y agoThe "root canal" side quest was definitely something. Kudos to author
- isoprophlex 1y ago> The only thing left to do was solder it up (not trivial, given that I’m trying to hit a 250 μm diameter target at the bottom of a 1.6mm deep hole). Shiiiit, absolutely heroic skill level.
- nine_k 1y agoPretty epic. A very impressive case of building one's own tools, or, rather, a one-off tool that seems to do a simple thing. The most impressive aspect is, of course, handling various issues that normally would require making a new PCB, but the author never retreated.
- kragen 1y agoI imagine he'll post the files, so they won't be a one-off.
- stephen_g 1y agoThey’re already linked from the article - https://github.com/azonenberg/triggercrossbar/ https://github.com/azonenberg/triggercrossbar/
- kragen 1y agoThanks! I had missed that!
- azonenberg 1y agoYep. Although given all of the bugs, I don't recommend anyone try to build one without forking and making substantial design changes :)
- a1o 1y agoThis is super impressive. Additionally, I had never heard about ngscopeclient before. Amazingly cool software!
- kragen 1y agoThis is very impressive.
- amluto 1y ago> My original plan had been to use their standard 1U folded sheet metal design, but I discovered too late, after boards were ordered, that it wasn’t going to work due to the 5mm corner mounting holes being inside the keepout area for the rear bend. I wonder if a less annoying solution would have been to omit the mounting holes and then drill and tap them after the fact, possibly at a slight angle if the metal is out of plane there.
- philipallstar 1y ago> Unfortunately, having all of the transceivers in a single quad was a bit limiting due to the 7 series clocking architecture: they share the same QPLL, which has to be at 10.3125 Gbps for 10Gbase-R operation. While the CPLLs can be configured freely, they have a lower Fmax which meant that the BERT / CDR trigger channels cannot operate at arbitrary frequencies above 6 Gbps (most notably, 8 Gbps operation for PCIe gen3 mode is not available). I'm glad someone understands this.
- stephen_g 1y agoThis one is especially tricky since even if you know what a phased lock loop (PLL) is, the terms CPLL and QPLL are specific to the arrangement of transceivers in these specific Xilinx FPGAs (7 series being one family of FPGAs which came before the UltraScale and then UltraScale+ series). There are four transceivers in a ‘quad’ which can either run from their ‘Channel PLL’ (CPLL) or the shared ‘Quad PLL’ that can run much faster to do basically double the line rate.
- azonenberg 1y agoYeah it's always tricky to decide how much detail to include in these posts. If I had gone on a whole explanation of the full 7 series GTX clocking architecture the post would easily have been another few pages in length.
- thomasjb 1y agoThis is a really beautiful bit of kit, really like the case and the thought given to signing, but the analog side is really impressive too. Would it be viable to use the same hardware as a base for an NTP server?
- azonenberg 1y agoYou could build an NTP server with much less horsepower (and of course without all of the high speed I/O etc). The ones from Leo Bodnar are decent.
- Liftyee 1y agoAmazing levels of depth and detail here. I wonder what sort of choices I need to make to eventually acquire a lab like this.
- thrtythreeforty 1y agoThe author is Andrew Zonenberg. For those unfamiliar, this qualifies as a "medium complexity" (!) project for him. His stuff is always a great read.