3 ms·
Shows what I know! I appreciate the correction. I wonder why the second example frustrates the optimization—but only on ARM? Also, why is it pushing r0 and r
by kragen 1y ago
Shows what I know! I appreciate the correction.
I wonder why the second example frustrates the optimization—but only on ARM? Also, why is it pushing r0 and r1? That's stupid. It's also stupid that it's using an extra `add` instruction to un-push them—if it doesn't want to overwrite r0, it could pop the worthlessly pushed values into r1 and r2, or r3 and r4. I tried a bunch of different versions of GCC on your example code, and they all seem to produce code that's bad in obvious ways, but they're different obvious ways.
- kragen 1y agoIn further thought, if you have an instruction cache, adding 8 to SP is a faster way to discard the two useless values than popping them into unused registers. So that part is arguably defensible. But why push them? There can't be a requirement for a 16-byte-aligned stack pointer at all times—the add would violate it.
- brucehoult 1y agoIt's definitely strange. And arm64 does it like the others.