3 ms·
If you can run a quad-core chip at 3 GHz, then there it is almost certainly feasible to run one core at 10 GHz. I suspect the real limit is in the size of the
by Daniel_Newby 14y ago
If you can run a quad-core chip at 3 GHz, then there it is almost certainly feasible to run one core at 10 GHz.
I suspect the real limit is in the size of the L1 and predecode caches. I expect they are limited by propagation delay, not transistor speed. The only way to get more cache is to use more cores.
- ajross 14y agoHeat transfer doesn't scale quite like that. Once the surface area gets beyond "tiny subcircuit" you're limited by the essentially 1D transfer "up" through the packaging and can't rely on the ability of the cooler silicon in the surrounding regions. One core is still a really big circuit. And yes, caches are big regions and hard to make faster synchronously. But you can treat this with pipelining -- that's one reason even the 32k L1 data cache in SNB/IVB has a 4 cycle (!) latency. Note that the even the gargantuan L3 cache on these chips (which is literally 1/3 of the die area) is still running at full speed, just with a ~30 cycle latency.
- Daniel_Newby 14y agoI was assuming silicon-on-sapphire soldered to a copper heat spreader. No numbers, but it feels plausible it could scale up. Wow. I did not know the L3 cache ran so fast.
- wtvanhest 14y agoLower energy consumption should also help the heat problem. Less waste in to heat.