> probably because the real hardware being used there is something like AVX and it can't be shared between all of the cores at the same time. That's not the ri

> probably because the real hardware being used there is something like AVX and it can't be shared between all of the cores at the same time. That's not the right explanation; each physical core has its own vector ALUs for handling SSE and AVX instructions. The chip's power budget is shared between cores, but not the physical transistors doing the vector operations.