3 ms·

Kind of weird that NOP actually slows down the pipeline, as I'd think that would be the easiest thing to optimize out of the pipeline, unless instruction fetch

by gwd 1y ago

Kind of weird that NOP actually slows down the pipeline, as I'd think that would be the easiest thing to optimize out of the pipeline, unless instruction fetch is one of the main limiting factors. Is it architecturally defined that NOP will slow down execution?

IcePic 1y ago
I think so, as in "make sure all other stuff has run before calling the NOP finished". Otherwise, it would just skip past it and it would have no effect if placed in a loop, so it would be eating memory for no use at all.
- bob1029 1y ago
  Eating memory alone may have the desired effect. The memory bandwidth of a cpu is not infinite.
- motorest 1y ago
  > I think so, as in "make sure all other stuff has run before calling the NOP finished". Is this related to speculative execution? The high level description sounds like NOP works as sync points.
Someone 1y ago
I think it would be easy, but still not worth the transistors. Think of it: what programs contain lots of NOPs? Who, desiring to write a fast program, sprinkles their code with NOPs? It’s not worth optimizing for situations that do not occur in practice. The transistors used to detect register clearing using XOR foo,foo, on the other hand, are worth it, as lots of code has that instruction, and removing the data dependency (the instruction technically uses the contents of the foo register, but its result is independent of its value) can speed up code a lot.
- adrian_b 1y ago
  On CPUs with variable instruction length, like the Intel/AMD CPUs, many programs have a lot of NOPs, which are inserted by the compiler for instruction alignment. However those NOPs are seldom executed frequently, because most are outside of loop bodies. Nevertheless, there are cases when NOPs may be located inside big loops, in order to align some branch targets to cache line boundaries. That is why many recent Intel/AMD CPUs have special hardware for accelerating NOP execution, which may eliminate the NOPs before reaching the execution units.
  - kevin_thibedeau 1y ago
    MIPS required NOP insertion for data hazards and the branch delay slot if a productive instruction couldn't be placed in the slot.
deleted 1y ago
[deleted]
pkhuong 1y ago
Yeah, just decode. But that's nice because the effect is independent of the backend's state.
adrian_b 1y ago
It depends on the CPU. On some CPUs a NOP might take the same time as an ADD and it might have the same throughput per clock cycle as ADD. However, there are CPUs among the Intel/AMD CPUs that can execute up to a certain number of consecutive NOPs in zero time, i.e. they are removed from the instruction stream before reaching the execution units. In general, no instruction set architecture specifies the time needed to execute an instruction. For every specific CPU model you must search its manual to find the latency and throughput for the instruction of interest, including for NOPs. Some CPUs, like the Intel/AMD CPUs, have multiple encodings for NOP, with different lengths in order to facilitate instruction alignment. In that case the execution time may be not the same for all kinds of NOPs.

by gwd 1y ago

IcePic 1y ago

I think so, as in "make sure all other stuff has run before calling the NOP finished". Otherwise, it would just skip past it and it would have no effect if placed in a loop, so it would be eating memory for no use at all.

bob1029 1y ago
Eating memory alone may have the desired effect. The memory bandwidth of a cpu is not infinite.
motorest 1y ago
> I think so, as in "make sure all other stuff has run before calling the NOP finished". Is this related to speculative execution? The high level description sounds like NOP works as sync points.

Someone 1y ago

I think it would be easy, but still not worth the transistors. Think of it: what programs contain lots of NOPs? Who, desiring to write a fast program, sprinkles their code with NOPs? It’s not worth optimizing for situations that do not occur in practice. The transistors used to detect register clearing using XOR foo,foo, on the other hand, are worth it, as lots of code has that instruction, and removing the data dependency (the instruction technically uses the contents of the foo register, but its result is independent of its value) can speed up code a lot.

adrian_b 1y ago
On CPUs with variable instruction length, like the Intel/AMD CPUs, many programs have a lot of NOPs, which are inserted by the compiler for instruction alignment. However those NOPs are seldom executed frequently, because most are outside of loop bodies. Nevertheless, there are cases when NOPs may be located inside big loops, in order to align some branch targets to cache line boundaries. That is why many recent Intel/AMD CPUs have special hardware for accelerating NOP execution, which may eliminate the NOPs before reaching the execution units.
- kevin_thibedeau 1y ago
  MIPS required NOP insertion for data hazards and the branch delay slot if a productive instruction couldn't be placed in the slot.

deleted 1y ago

[deleted]

pkhuong 1y ago

Yeah, just decode. But that's nice because the effect is independent of the backend's state.

adrian_b 1y ago

It depends on the CPU. On some CPUs a NOP might take the same time as an ADD and it might have the same throughput per clock cycle as ADD. However, there are CPUs among the Intel/AMD CPUs that can execute up to a certain number of consecutive NOPs in zero time, i.e. they are removed from the instruction stream before reaching the execution units. In general, no instruction set architecture specifies the time needed to execute an instruction. For every specific CPU model you must search its manual to find the latency and throughput for the instruction of interest, including for NOPs. Some CPUs, like the Intel/AMD CPUs, have multiple encodings for NOP, with different lengths in order to facilitate instruction alignment. In that case the execution time may be not the same for all kinds of NOPs.