How are all the features of an architecture like this utilized? Does the hardware automatically take advantage of all the cache, RAM, threads, etc., or are main

How are all the features of an architecture like this utilized? Does the hardware automatically take advantage of all the cache, RAM, threads, etc., or are mainframe applications specifically written with chunks of low-level assembly to optimize for the specific features of the chip and supporting hardware? The devs that write the compilers must be geniuses.