4 ms·

Libre-Chip Awarded NLnet Grant to Prototype a CPU Isn't Vulnerable to Spectre

25 points by Bender 1y ago

dutchmartin 1y ago
Interesting to see, hope they make progress on preventing the spectre attacks, since these are still relevant today. See this paper that was presented at the WHY2025 hacker camp: https://openreview.net/pdf?id=4tDNvQe2G0 https://openreview.net/pdf?id=4tDNvQe2G0
westurner 1y ago
Speculative execution > Variants,: https://en.wikipedia.org/wiki/Speculative_execution https://en.wikipedia.org/wiki/Speculative_execution Transient execution CPU vulnerability: https://en.wikipedia.org/wiki/Transient_execution_CPU_vulnerability https://en.wikipedia.org/wiki/Transient_execution_CPU_vulner... Does RISC-V have speculative execution? A RISC-V CPU out of graphene would be more efficient.
- westurner 1y ago
  openhwgroup has open Verilog implementations of RISC-V cores from 2 stages through 6 stages that will boot Linux: https://github.com/openhwgroup https://github.com/openhwgroup There are various optional feature flags for RISC-V. The RISC-V open ISA is probably advantageous especially for research implementations.
yencabulator 1y ago
More information: https://libre-chip.org/first_arch/index.html https://libre-chip.org/first_arch/index.html https://web.archive.org/web/20201021124234/https://bugs.libre-soc.org/show_bug.cgi?id=209 https://web.archive.org/web/20201021124234/https://bugs.libr... https://web.archive.org/web/20240610080828/https://groups.google.com/g/comp.arch/c/1OvTXelf5TE/m/EMgX17YEBAAJ https://web.archive.org/web/20240610080828/https://groups.go... https://danluu.com/branch-prediction/ https://danluu.com/branch-prediction/ > One idea I had for making a spectre-proof speculative execution engine is to build a theoretical model CPU such that it compares a branch oracle to the results of its branch prediction unit and takes the amount of time needed by the misprediction penalty when the branch predictor mispredicts, but doesn't actually execute any mispredicted instructions. This makes the model CPU unable to have spectre-style vulnerabilities since it doesn't do any actual speculative execution. > Then, a physical CPU is built using the exact same design (where every instruction and every cache state change completes at the exact same clock cycle as the corresponding instruction in the theoretical model) but using speculative execution instead of the branch oracle. This gives a physical cpu that can be proven to not have any timing vulnerabilities that the model CPU doesn't have (ruling out spectre-style vulnerabilities) by proving that it follows the same steps as the model CPU.

25 points by Bender 1y ago

Interesting to see, hope they make progress on preventing the spectre attacks, since these are still relevant today. See this paper that was presented at the WHY2025 hacker camp: https://openreview.net/pdf?id=4tDNvQe2G0 https://openreview.net/pdf?id=4tDNvQe2G0

westurner 1y ago

Speculative execution > Variants,: https://en.wikipedia.org/wiki/Speculative_execution https://en.wikipedia.org/wiki/Speculative_execution Transient execution CPU vulnerability: https://en.wikipedia.org/wiki/Transient_execution_CPU_vulnerability https://en.wikipedia.org/wiki/Transient_execution_CPU_vulner... Does RISC-V have speculative execution? A RISC-V CPU out of graphene would be more efficient.

westurner 1y ago
openhwgroup has open Verilog implementations of RISC-V cores from 2 stages through 6 stages that will boot Linux: https://github.com/openhwgroup https://github.com/openhwgroup There are various optional feature flags for RISC-V. The RISC-V open ISA is probably advantageous especially for research implementations.

yencabulator 1y ago

More information: https://libre-chip.org/first_arch/index.html https://libre-chip.org/first_arch/index.html https://web.archive.org/web/20201021124234/https://bugs.libre-soc.org/show_bug.cgi?id=209 https://web.archive.org/web/20201021124234/https://bugs.libr... https://web.archive.org/web/20240610080828/https://groups.google.com/g/comp.arch/c/1OvTXelf5TE/m/EMgX17YEBAAJ https://web.archive.org/web/20240610080828/https://groups.go... https://danluu.com/branch-prediction/ https://danluu.com/branch-prediction/ > One idea I had for making a spectre-proof speculative execution engine is to build a theoretical model CPU such that it compares a branch oracle to the results of its branch prediction unit and takes the amount of time needed by the misprediction penalty when the branch predictor mispredicts, but doesn't actually execute any mispredicted instructions. This makes the model CPU unable to have spectre-style vulnerabilities since it doesn't do any actual speculative execution. > Then, a physical CPU is built using the exact same design (where every instruction and every cache state change completes at the exact same clock cycle as the corresponding instruction in the theoretical model) but using speculative execution instead of the branch oracle. This gives a physical cpu that can be proven to not have any timing vulnerabilities that the model CPU doesn't have (ruling out spectre-style vulnerabilities) by proving that it follows the same steps as the model CPU.