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You might want to double check that. I would assume you are getting caught up on the gates of memory cells being capacitive and holding a charge. But both memor

You might want to double check that. I would assume you are getting caught up on the gates of memory cells being capacitive and holding a charge. But both memory types use FET technology, and saying FETs use static electricity is sort of a stretch.

kazinator 1y ago
- There exists TTL SRAM. - The state in a SRAM cell is maintained by mutual feedback of two cross-coupled amplifier-like circuits. The currents involved may be low in the case of CMOS, but that's immaterial to the design that it's not simply static electricity representing the 0 or 1 state. But power must continue to be supplied for the state to persist. - The state of a DRAM call is actually charge on a capacitor. It leaks and so DRAM requires refresh. The dynamic/static refers to the need or no need for refresh.
- adrian_b 1y ago
  In a true CMOS cell (i.e. not in the so-called 4-transistor CMOS SRAM cell, which is actually an NMOS RAM cell), the transistors have leakage currents, but the existence of those leakage currents is irrelevant for how the RAM cell functions. The storage capability of such a CMOS SRAM cell is determined by the electric charges stored in the gate capacitances of the transistors. If the transistors had no leakage currents, the state of the memory cell would be maintained indefinitely, without any current. As it is, the leakage currents slowly discharge the gate capacitances, but then the positive feedback very slightly opens some of the transistors, enough to pass currents that compensates the effect of the leakage currents on the electric charge stored on the gate capacitances. So the existence of currents in a true CMOS SRAM cell is a second order effect that would not be present with ideal components and it is not inherently necessary for the function of the cell, like it is for NMOS/PMOS/bipolar SRAM cells. Designing the value of the cell current in a non-CMOS cell is very important for determining the cell characteristics. For designing a CMOS cell, the leakage currents have little importance, even if they will determine the power consumption of the cell, when idle. The information storage capability of a CMOS cell is determined by the electric charge stored on the gate capacitances, which must be great enough to prevent changes in the gate voltages due to electrical noise or radiation events. Both in DRAM cells and in true CMOS SRAM cells the information is stored as electric charge on capacitors. In a DRAM cell the charge decays continuously due to leakage currents, until it is refreshed. In a CMOS SRAM cell, the decay of the charge is prevented by the positive feedback circuit, which compensates the leakage currents, so no refresh is necessary, at the cost of a more complex memory cell.

kazinator 1y ago

- There exists TTL SRAM. - The state in a SRAM cell is maintained by mutual feedback of two cross-coupled amplifier-like circuits. The currents involved may be low in the case of CMOS, but that's immaterial to the design that it's not simply static electricity representing the 0 or 1 state. But power must continue to be supplied for the state to persist. - The state of a DRAM call is actually charge on a capacitor. It leaks and so DRAM requires refresh. The dynamic/static refers to the need or no need for refresh.

adrian_b 1y ago
In a true CMOS cell (i.e. not in the so-called 4-transistor CMOS SRAM cell, which is actually an NMOS RAM cell), the transistors have leakage currents, but the existence of those leakage currents is irrelevant for how the RAM cell functions. The storage capability of such a CMOS SRAM cell is determined by the electric charges stored in the gate capacitances of the transistors. If the transistors had no leakage currents, the state of the memory cell would be maintained indefinitely, without any current. As it is, the leakage currents slowly discharge the gate capacitances, but then the positive feedback very slightly opens some of the transistors, enough to pass currents that compensates the effect of the leakage currents on the electric charge stored on the gate capacitances. So the existence of currents in a true CMOS SRAM cell is a second order effect that would not be present with ideal components and it is not inherently necessary for the function of the cell, like it is for NMOS/PMOS/bipolar SRAM cells. Designing the value of the cell current in a non-CMOS cell is very important for determining the cell characteristics. For designing a CMOS cell, the leakage currents have little importance, even if they will determine the power consumption of the cell, when idle. The information storage capability of a CMOS cell is determined by the electric charge stored on the gate capacitances, which must be great enough to prevent changes in the gate voltages due to electrical noise or radiation events. Both in DRAM cells and in true CMOS SRAM cells the information is stored as electric charge on capacitors. In a DRAM cell the charge decays continuously due to leakage currents, until it is refreshed. In a CMOS SRAM cell, the decay of the charge is prevented by the positive feedback circuit, which compensates the leakage currents, so no refresh is necessary, at the cost of a more complex memory cell.