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There are no guarantees even if everything operates on the same core. Rust docs have some details: https://doc.rust-lang.org/stable/core/arch/x86_64/fn._mm_sfen
by m0th87 1y ago
There are no guarantees even if everything operates on the same core. Rust docs have some details: https://doc.rust-lang.org/stable/core/arch/x86_64/fn._mm_sfence.html#safety-of-non-temporal-stores https://doc.rust-lang.org/stable/core/arch/x86_64/fn._mm_sfe...
- Sesse__ 1y agoDo you have any Intel references for it? I mean, Rust has its own memory model and it will not always give the same guarantees as when writing assembler.
- m0th87 1y agohttps://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sfence&ig_expand=5873 https://www.intel.com/content/www/us/en/docs/intrinsics-guid... Intel's docs are unfortunately spartan, but the guarantees around program order is a hint that this is what it does.
- Sesse__ 1y agoThat doc is about visibility _outside the core_ (“globally visible”), so it's not what I'm looking for. Similarly, if I look up MOVNTDQ in the Intel manuals (https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-2b-manual.pdf https://www.intel.com/content/dam/www/public/us/en/documents...), they say: “Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with the SFENCE or MFENCE instruction should be used in conjunction with VMOVNTDQ instructions if multiple processors might use different memory types to read/write the destination memory locations” Note _if multiple processors_.
- deleted 1y ago[deleted]