I think the point of this project hinges on putting the CPU arch down to the FPGA - buying prebaked silicon in the form of an off the shelf risc-v CPU defeats m

I think the point of this project hinges on putting the CPU arch down to the FPGA - buying prebaked silicon in the form of an off the shelf risc-v CPU defeats most of the purpose. The purpose being everything can be built from the bottom up and at no point is any part of it out of the scope of inspection. You never actually know what is spun into a that PIC64GX1000 because you didn't place and route and oversee the fab yourself. Just because an ISA is 'open' like risc-v does not mean you know how it was implemented on-die. Having all the verilog and using Yosys+nextpnr to generate the layout for the FPGA is (about) as close to knowing the provenance of the whole stack as you can ever get.