To me it would be equivalent of saying "Yeah C sucks and is verbose, Let's make a C generator using python. Look ma I can even make generic data structures and

To me it would be equivalent of saying "Yeah C sucks and is verbose, Let's make a C generator using python. Look ma I can even make generic data structures and function". That is to say I think the generator approach is a dead end. A local optimum before we move to real languages. Sure it's a lot better than bare Verillog/SV/VHDL but that bar is very low. I believe gaving native language contructs that supports designing and simulating hardware is much more powerful.