4 ms·

For EDA, gate-all-around technologies used in 2nm processes are banned from export by ITAR. This applies to device electrical modeling as well as physical desig

by vFunct 1y ago

For EDA, gate-all-around technologies used in 2nm processes are banned from export by ITAR. This applies to device electrical modeling as well as physical design layout rules. You won’t find these GAA in KiCAD or OpenROAD. I think for this case though it was specifically because Cadence sold a commercial product to a banned entity, instead of anything technology related.

15155 1y ago
> You won’t find these GAA in KiCAD or OpenROAD. Is this actually because of legal requirements, or because of reality? Nobody with access to a bleeding-edge node is using vastly inferior FOSS tools that can't actually work with a brand new fab PDK (which was produced specifically for Synopsys or Cadence tools.)
- deleted 1y ago
  [deleted]