Manufacturers don't lie about how many clock cycles Dhrystone or Coremark or SPEC takes on their design. The first two can be checked at the verilator (or comm

Manufacturers don't lie about how many clock cycles Dhrystone or Coremark or SPEC takes on their design. The first two can be checked at the verilator (or commercial equivalent) stage, and SPEC in FPGA, both long before physical chips. The only things in doubt are: - whether they hit the hoped-for MHz - whether the code you want to run has the same characteristics as their benchmark For example SG2044 GeekBench results have been appearing on the site from time to time for more than half a year now. GB as a whole is pretty much worthless for what I care about, but the Clang test within it aligns closely with what I do, including the rqtio between multi-thread and single-thread.