Instead of large cores operating mostly independently in parallel (with some few standardized hardwired pipeline steps per core), … You have many more very sma

Instead of large cores operating mostly independently in parallel (with some few standardized hardwired pipeline steps per core), … You have many more very small ALU cores, configurable into longer custom pipelines with each step more or less as wide/parallel or narrow as it needs to be for each step. Instead of streaming instructions over & over to large cores, you use them to set up those custom pipeline circuits, each running until it’s used up its data. And you also have some opportunity for multiple such pipelines operating in parallel depending on how many operations (tiles) each pipeline needs.