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> used to be a crown-jewel of US tech I feel like x86 itself is kinda legacy tech. So while AMD has made advancements, they're somewhat in the same boat as In
by VWWHFSfQ 1y ago
> used to be a crown-jewel of US tech
I feel like x86 itself is kinda legacy tech. So while AMD has made advancements, they're somewhat in the same boat as Intel.
It seems like NVIDIA and Micron are the real "crown jewels" of US tech
- sho_hn 1y agoTech-wise places too much premium on the ISA. Modern processor design is fairly orthogonal to the ISA being exposed. Intel could make exciting RISC-V relatively quickly if they wanted to; what stops them and other companies like this is the strategic asset they perceive their existing ecosystem as.
- codedokode 1y agoI don't think so. For example, if an ISA requires a strict memory ordering, this makes the architecture more complicated than an ISA with relaxed memory ordering, although the latter is a pain to write code for.
- protimewaster 1y agoThere's a nice interview with Mike Clark where he talks about this a bit. His take basically matches this. He says that, in his view, any efficiency benefits of ARM are just that's been the market for ARM. In his view, if x86 had a market motive for ARM levels of efficiency, they'd be able to deliver it. But, historically, the x86 market wants performance more than efficiency, so that's what it gets. https://www.computerenhance.com/p/an-interview-with-zen-chief-architect https://www.computerenhance.com/p/an-interview-with-zen-chie...
- tester756 1y agoISA is irrelevant It's like saying that programming language syntax/keywords are better than the other. Everything is about compiler, lib, runtime, etc. https://chipsandcheese.com/p/arm-or-x86-isa-doesnt-matter https://chipsandcheese.com/p/arm-or-x86-isa-doesnt-matter Also some people say that RISC-V is the way to go
- riehwvfbk 1y agoAnd yet Itanium flopped.
- lallysingh 1y agoThey required unreasonable things from the compiler for instruction scheduling.
- ben-schaaf 1y agoBy all accounts I can find Itanium performance was good, perhaps even great when writing assembly. It seems to reinforce the point that ISA doesn't really matter. But let's be clear: Of course ISA matters. It's just as trivial to make a bad ISA as it is a bad syntax. But does the ISA of modern superscalar processors matter? Probably a bit, but certainly not a whole lot.
- dboreham 1y agoIt wasn't good vs peer competitors at the time (HP-PA, DEC Alpha, IBM RS/6000, even MIPS). And it was very expensive. Huge die. It was an expensive, strange thing, that didn't have the necessary 2X peer performance advantage to offset those issues.
- ajross 1y agoBut not because of its ISA. I mean, to first approximation everything is a "flop" in semiconductor architectures (or really in tech in general). The population of genuinely successful products is a tiny fraction of the stuff people tried to sell. In this particular case: ia64 leaned hard into wide VLIW in an era where growing transistor budgets made it possible to decode and issue traditional instructions in parallel[1]. The Itaniums really were fine CPUs, they just weren't particularly advantageous relative to the P6 cores against which they were competing, so no one bought them. [1] In some sense, VLIW won as a matter of pipeline architecture, it only lost as a design point in ISA specs. Your Macbook is issuing 10 arm64 instructions every cycle, and it doesn't need to futz with the instruction format to do it.
- sapiogram 1y ago> I feel like x86 itself is kinda legacy tech. The impact of ISA is overrated, it's much more important that the ISA continues to grow and adapt as CPUs get larger.
- FuriouslyAdrift 1y agomodern x86 chips (for a long time really) are hybrid CISC/RISC at the hardware level. It's at the microcode that the ISA lives and that's changeable.
- cesarb 1y ago> It's at the microcode that the ISA lives and that's changeable. No, it's not. In modern high-speed CPUs, many instructions are decoded directly, without going through the microcode engine. In fact, on several modern Intel CPUs, only one of the instruction decoders can run microcode ("complex") instructions, while all the other decoders can only run non-microcode ("simple") instructions. It would be more precise to say that it's at the "front-end" part of the core (where the decoders are) that the ISA lives, but even that's not quite true; many ISAs have peculiarities which affect beyond that, like flags on x86.
- FuriouslyAdrift 1y agoI think I am conflating micro-ops with microcode and your above comment is the correct way of thinking about it.
- FuriouslyAdrift 1y agoIt was my understanding that even direct coded instructions are still translated by the microcode into the actual signals to allow for errata patching since the P6 architecture and to maintain a common ISA target within a family of processors with diffferent physical characteristics.