I taught Digital Design this semester - all models output nonsensical VHDL. The only exception is reciting “canonical” components available on technical and sci

I taught Digital Design this semester - all models output nonsensical VHDL. The only exception is reciting “canonical” components available on technical and scientific literature (e.g., [1]). [1] https://docs.amd.com/r/en-US/ug901-vivado-synthesis/Flip-Flop-Registers-with-Rising-Edge-Clock-Coding-VHDL-Example https://docs.amd.com/r/en-US/ug901-vivado-synthesis/Flip-Flo...