I only meant that MIPS got rid of the "without interlocking pipeline stages" in the R4000, not the other stuff. I was just saying that was a weird architectural

I only meant that MIPS got rid of the "without interlocking pipeline stages" in the R4000, not the other stuff. I was just saying that was a weird architectural feature not unlike BDSs and register windows. BTW, tagged integers are still in SPARC but just for 32b. I'll have to look up the nifty trick. I have a soft spot for delay slots.