4 ms·
… without interlocked pipeline stages was an early weird RISC bet not unlike register windows, branch delay slots or tagged integers. They abandoned it in R4000
by CalChris 1y ago
… without interlocked pipeline stages was an early weird RISC bet not unlike register windows, branch delay slots or tagged integers. They abandoned it in R4000.
- gomijacogeo 1y agoNo, they got rid of the load delay slot in MIPS II. While not required in later ABIs, they kept the branch delay slot for backwards compatibility. MIPS32/MIPS64, which came out much later, also had several new branch instructions without delay slots. One (probably the only) nifty thing the branch delay slot allowed was in the user-space threads implementation, you didn't have to burn a register for the jump to another thread, you'd do the branch and then clobber the register with the last bit of the jumped-to thread's context. Kinda fiendishly clever.
- CalChris 1y agoI only meant that MIPS got rid of the "without interlocking pipeline stages" in the R4000, not the other stuff. I was just saying that was a weird architectural feature not unlike BDSs and register windows. BTW, tagged integers are still in SPARC but just for 32b. I'll have to look up the nifty trick. I have a soft spot for delay slots.