4 ms·
For DDR4 it's 17 vs 16 memory cycles for the data burst phase.
by bobmcnamara 1y ago
For DDR4 it's 17 vs 16 memory cycles for the data burst phase.
- ryao 1y agoIf you measure memory access time in CPU cycles, you would see that 150 cycles is the ballpark. 16 cycles would be closer to L2 cache.