>Intel/AMD difference on IP rollover Never read about this before, but the explanation in the wiki seems made up to me. The way it's described makes it sound l

>Intel/AMD difference on IP rollover Never read about this before, but the explanation in the wiki seems made up to me. The way it's described makes it sound like yet another legacy "feature" that's been there forever, but older x86 CPUs did not (generally) behave like this. The 8086 (and 186) did wrap around of course, because they had no memory protection and only 20 address lines. But I know for a fact that the 286 would fault and invoke interrupt 0Dh [1][2]. I'm fairly certain the 386 did so as well. Segment limits are enforced even in real mode, and at reset they are initialized to 64K. Or is the CPU already in protected mode, and segment limit set to 4G? In that case Intel and AMD might differ. (The 286 was 16-bit, so 64K was the maximum there. Arguably, the "correct" behavior for 386+ would be to do the same thing when the limit is 4G) What it says about opcode FFFFh however is even more likely to be wrong. That opcode has always been undefined, only the original 8086/8088 ("1970s stuff") would execute it, but as PUSH DI instead of NOP. It's not impossible that Intel made the decision to interpret it as NOP in some later generation, without ever documenting it. But I just tried this on my modern-ish Intel machine, and it aborted with "Illegal instruction". [1] third post in https://forum.vcfed.org/index.php?threads/286-cpu-experiments.1253659/ https://forum.vcfed.org/index.php?threads/286-cpu-experiment... [2] also note it isn't a double fault (interrupt 8). And shutdown occurs on a "triple fault", i.e. when the CPU fails to invoke the double fault handler.