3 ms·

Whoa, had no idea this existed. Wild stuff. Might be "somewhat" confusing to read assembler code like that without knowing about this particular technique..

chasil 1y ago
Allow me to introduce you to register windows. https://www.jwhitham.org/2016/02/risc-instruction-sets-i-have-known-and.html https://www.jwhitham.org/2016/02/risc-instruction-sets-i-hav...
- apaprocki 1y ago
  Both register windows and the delay slot exist on SPARC processors, which you’re much more likely to run into in a data center (running open-source software). Itanium was the really odd one — it not only used register windows but could offload some of the prior windows onto the heap. Most people would probably never notice… unless you’re trying to get a conservative scanning GC working and are stumped why values in some registers seem to not be traced…
  - burnt-resistor 1y ago
    Pour one out for Itanium. It tried to make the panacea of VLIW and branch hints work, but it didn't pan out.
    - chasil 1y ago
      From an interview with Bob Colwell: 'Anyway this chip architect guy is standing up in front of this group promising the moon and stars. And I finally put my hand up and said I just could not see how you're proposing to get to those kind of performance levels. And he said well we've got a simulation, and I thought Ah, ok. That shut me up for a little bit, but then something occurred to me and I interrupted him again. I said, wait I am sorry to derail this meeting. But how would you use a simulator if you don't have a compiler? He said, well that's true we don't have a compiler yet, so I hand assembled my simulations. I asked "How did you do thousands of line of code that way?" He said “No, I did 30 lines of code”. Flabbergasted, I said, "You're predicting the entire future of this architecture on 30 lines of hand generated code?" [chuckle], I said it just like that, I did not mean to be insulting but I was just thunderstruck. Andy Grove piped up and said "we are not here right now to reconsider the future of this effort, so let’s move on".' https://www.sigmicro.org/media/oralhistories/colwell.pdf https://www.sigmicro.org/media/oralhistories/colwell.pdf
      - panick21_ 1y ago
        Sun had some funny stories around this too. When they came up with their multi-core system, and they used code from 10-15 years earlier for traces. And then said 'well, nobody actually uses floating code' so we don't need it. Of course over those 10 years Floating point became much more common and stand. Leading to a chip that had one FPU for 8 cores, basically meaning, even minimal floating point would destroy concurrency. Arguably Sun had already lose the chip war and this was just making them fall behind further. They did market it in quite well. And a lesser known thing that I couldn't find much information on is that Sun also worked on VLIW chip during the 90s. Apparently Bill Joy was convinced that VLIW was the future so they did a VLIW chip, and the project was lead by David Ditzel. As far as I am aware this was never released. If any Sun veterans have any idea about this, I would love to know.
        chasil 1y ago
        As far as the single FPU that you mention, the T1 is an open-source CPU. https://www.oracle.com/servers/technologies/opensparc-t1-page.html https://www.oracle.com/servers/technologies/opensparc-t1-pag... The T2 is also open, and places an FPU in each core. https://www.oracle.com/servers/technologies/opensparc-t2-page.html https://www.oracle.com/servers/technologies/opensparc-t2-pag... When there is such complaint about closed firmware in the Raspberry Pi, and the risk of the Intel ME and other closed CPU features, I wonder why these open designs are ignored. Yes, the performance and power consumption would be poor by modern standards.
        panick21_ 1y ago
        These designed are not ignored. They were used for a few things here and there. But the usefulness of 'over the wall' open code without backing is always a bit limited and for processors that cost 100k to tap out, even more so. By now there are much better more modern design out-there and for RISC-V.
        jecel 1y ago
        Sun's project was an attempt to have a high performance Java processor to replace the simpler PicoJava: https://en.wikipedia.org/wiki/MAJC https://en.wikipedia.org/wiki/MAJC
    - chithanh 1y ago
      VLIW is maybe cool, but people will be relieving themselves on EPIC's grave for the pain that it inflicted on them. Like if you tried to debug a software crash on Itanium. The customer provided core dump was useless as you could not see what was going on. Intel added a debug mode to their compilers which disabled all that EPIC so hopefully you could reproduce the crash there, or on other CPU architectures. Otherwise you were basically screwed.
      - burnt-resistor 1y ago
        EPIC :nauseous face emoji: That HP-Intel arrangement was weird. One time, an Intel-badged employee came out to change a tape drive on a (Compaq->HP->HPE) Compaq SSL2020 tape robot. Okay, I guess they shared employees. ¯\_(ツ)_/¯
- burnt-resistor 1y ago
  I was going to make a reference to Patterson & Hennessy, but it's too bad that the 5th and later editions are hidden behind a DRM paywall. You don't "own" books anymore.
bobmcnamara 1y ago
Many assemblers had an option to reorder on assembly so you could write it normally, while only taking care to avoid hazards near branches. At least one toolchain would just pad the slots with nops

chasil 1y ago

Allow me to introduce you to register windows. https://www.jwhitham.org/2016/02/risc-instruction-sets-i-have-known-and.html https://www.jwhitham.org/2016/02/risc-instruction-sets-i-hav...

apaprocki 1y ago
Both register windows and the delay slot exist on SPARC processors, which you’re much more likely to run into in a data center (running open-source software). Itanium was the really odd one — it not only used register windows but could offload some of the prior windows onto the heap. Most people would probably never notice… unless you’re trying to get a conservative scanning GC working and are stumped why values in some registers seem to not be traced…
- burnt-resistor 1y ago
  Pour one out for Itanium. It tried to make the panacea of VLIW and branch hints work, but it didn't pan out.
  - chasil 1y ago
    From an interview with Bob Colwell: 'Anyway this chip architect guy is standing up in front of this group promising the moon and stars. And I finally put my hand up and said I just could not see how you're proposing to get to those kind of performance levels. And he said well we've got a simulation, and I thought Ah, ok. That shut me up for a little bit, but then something occurred to me and I interrupted him again. I said, wait I am sorry to derail this meeting. But how would you use a simulator if you don't have a compiler? He said, well that's true we don't have a compiler yet, so I hand assembled my simulations. I asked "How did you do thousands of line of code that way?" He said “No, I did 30 lines of code”. Flabbergasted, I said, "You're predicting the entire future of this architecture on 30 lines of hand generated code?" [chuckle], I said it just like that, I did not mean to be insulting but I was just thunderstruck. Andy Grove piped up and said "we are not here right now to reconsider the future of this effort, so let’s move on".' https://www.sigmicro.org/media/oralhistories/colwell.pdf https://www.sigmicro.org/media/oralhistories/colwell.pdf
    - panick21_ 1y ago
      Sun had some funny stories around this too. When they came up with their multi-core system, and they used code from 10-15 years earlier for traces. And then said 'well, nobody actually uses floating code' so we don't need it. Of course over those 10 years Floating point became much more common and stand. Leading to a chip that had one FPU for 8 cores, basically meaning, even minimal floating point would destroy concurrency. Arguably Sun had already lose the chip war and this was just making them fall behind further. They did market it in quite well. And a lesser known thing that I couldn't find much information on is that Sun also worked on VLIW chip during the 90s. Apparently Bill Joy was convinced that VLIW was the future so they did a VLIW chip, and the project was lead by David Ditzel. As far as I am aware this was never released. If any Sun veterans have any idea about this, I would love to know.
      - chasil 1y ago
        As far as the single FPU that you mention, the T1 is an open-source CPU. https://www.oracle.com/servers/technologies/opensparc-t1-page.html https://www.oracle.com/servers/technologies/opensparc-t1-pag... The T2 is also open, and places an FPU in each core. https://www.oracle.com/servers/technologies/opensparc-t2-page.html https://www.oracle.com/servers/technologies/opensparc-t2-pag... When there is such complaint about closed firmware in the Raspberry Pi, and the risk of the Intel ME and other closed CPU features, I wonder why these open designs are ignored. Yes, the performance and power consumption would be poor by modern standards.
        panick21_ 1y ago
        These designed are not ignored. They were used for a few things here and there. But the usefulness of 'over the wall' open code without backing is always a bit limited and for processors that cost 100k to tap out, even more so. By now there are much better more modern design out-there and for RISC-V.
      - jecel 1y ago
        Sun's project was an attempt to have a high performance Java processor to replace the simpler PicoJava: https://en.wikipedia.org/wiki/MAJC https://en.wikipedia.org/wiki/MAJC
  - chithanh 1y ago
    VLIW is maybe cool, but people will be relieving themselves on EPIC's grave for the pain that it inflicted on them. Like if you tried to debug a software crash on Itanium. The customer provided core dump was useless as you could not see what was going on. Intel added a debug mode to their compilers which disabled all that EPIC so hopefully you could reproduce the crash there, or on other CPU architectures. Otherwise you were basically screwed.
    - burnt-resistor 1y ago
      EPIC :nauseous face emoji: That HP-Intel arrangement was weird. One time, an Intel-badged employee came out to change a tape drive on a (Compaq->HP->HPE) Compaq SSL2020 tape robot. Okay, I guess they shared employees. ¯\_(ツ)_/¯
burnt-resistor 1y ago
I was going to make a reference to Patterson & Hennessy, but it's too bad that the 5th and later editions are hidden behind a DRM paywall. You don't "own" books anymore.

bobmcnamara 1y ago

Many assemblers had an option to reorder on assembly so you could write it normally, while only taking care to avoid hazards near branches. At least one toolchain would just pad the slots with nops