You don't need to simulate the design completely/simultaneously. The FPGA sim implementation might only contain 1 CUDA SM, for instance. For large ASIC designs

You don't need to simulate the design completely/simultaneously. The FPGA sim implementation might only contain 1 CUDA SM, for instance. For large ASIC designs like this, companies often use numerous (12+) FPGAs connected via transceivers on dedicated simulation boards.