4 ms·It would be nice to have a simulator like Verilator for VHDL.by thijson 1y agoIt would be nice to have a simulator like Verilator for VHDL.kvemkon 1y agoThere is mature GHDL https://github.com/ghdl/ghdl https://github.com/ghdl/ghdl and rather new NVC https://github.com/nickg/nvc https://github.com/nickg/nvc.thijson 1y agoI was aware of GHDL. NVC looks like it's potentially more performant.rluoy 1y agoLLVM never works in EDA.