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SUS Lang: The SUS Hardware Description Language
- randomNumber7 1y agoI really feel that hardware description languages could need some fresh air (especially the tooling), but on the other hand it must be insanely difficult to come up with s.th. that can compete with the major players.
- mdhb 1y agoAlso worth checking out is this project from Intel: https://github.com/intel/rohd/tree/main https://github.com/intel/rohd/tree/main > The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
- 1024bees 1y agoA point of frustration for newer languages, that sus continues, is the lack of thought towards simulation and testbench design, and how it integrates with the language. While it would be nice to have more elegant support for "modern" codegen in the sv/verilog/vhdl, the real unergonomic experiences are test bench design and integration. The only real options are (for sv, verilog, I have less experience with vhdl): use verilator and write your tb in cpp, use verilator and then write your testbench in cocotb, or you work at a chip design company and use one of the big 3's compilers and maybe you use UVM or cocotb. Verilator and cocotb are okay, but you're crossing a language boundar(ies) and referencing generated code -- it is both mechanical and complex to get any design working with it. If sus had first class interfaces to create testbenches that could map to UVM or verilator, it would be much more interesting. Spade does some interesting things by having its own package manager, but doesn't (afaik) expose a ton within the language itself
- artemonster 1y agoas a HW designer that writes RTL for living I will repeat this 150 times and will put this on my gravestone: WE DONT NEED ANOTHER SHMANCY HDL. really. existing ones are moooooorrreeee than fine. our tools suck, verification sucks. your design complexity is entirely limited by your verification capabilities (and automation infra). having fancy constructs for CDC or pipelining in HDL is utterly useless, especially that CDC checking is done by special tools that do it nearly perfect with a bit of constraints.
- bgnn 1y agoTotally agreed. This is the problem of academia unfortunately, the people working on these have no experience in designing complex chips and facing the real limitations. We are so stupidly limited by our EDA tooling and infrastructure. I wish these efforts would have been put to use in that front.
- thijson 1y agoIt would be nice to have a simulator like Verilator for VHDL.
- almostgotcaught 1y ago> We are so stupidly limited by our EDA tooling and infrastructure. The problem that no one will ever solve is there's no gcc equivalent to NXT. Everything is downstream of that problem.
- artemonster 1y agoare you sure it will do anything at all? I am not. The current setup, while objectively sucks for engineers is still quite capable and it *works*. we are far from reaching limits of what is capable to design and tape with current flows. frontend money aspect for tools is still peanuts in comparison to backend and actual fabrication, so it will not generate a renaissance era like gcc did for software
- ei8ths 1y agothis whole thing is sus...
- ForgotMyUUID 1y agoHi everyone! Question for Verilog/VHDL Profis: What are your favorite documenting tools? Is there a way to automatically generate API for a project? I am looking for something like autodoc from sphinx but for Verilog.
- artemonster 1y agowhat do you mean by "api for a project" in a context of digital hardware design?
- hulitu 1y ago> SUS Lang: The SUS Hardware Description Language SUS ? Single UNIX Specification ?