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The profile includes not just additional instructions but also architectural requirements that can't be emulated. The size of cache lines and reservation sets m
by Findecanor 1y ago
The profile includes not just additional instructions but also architectural requirements that can't be emulated. The size of cache lines and reservation sets must be 64 bytes (there is no instruction to query it, like there is on ARM).
Data-independent execution latency is important for protecting cryptography against timing attacks.
Those were already in RVA22, and the difference from that to RVA23 could probably be emulated with traps though.
However, I think that some of the new instructions in RVA23 may potentially become very common in some binaries later on and could possibly trap so often that they would slow down those programs considerably.
- bobmcnamara 1y ago> The size of cache lines and reservation sets must be 64 bytes (there is no instruction to query it, like there is on ARM) Thank goodness. What a colossal PITA trying to account for that across cluster switches.
- anticensor 1y agoCouldn't one completely disable cache thereby forcing a worst-case timing?
- brucehoult 1y ago> the difference from that to RVA23 could probably be emulated with traps though There is no way you want to be trapping basic things such as `c.lb{u}` and `c.sb` and `c.{s,z}ext.{b,h,w}` which are going to be thoroughly mixed in all over the place.