3 ms·

I'm assuming this space has already been heavily optimized by the Bitcoin miners on their way to ASICs.

picture 1y ago
Yes, hard silicon will be another magnitude more performant than FPGAs and GPUs, but ASICs properly take on negative value when they're no longer profitable to mine with. (Note that efficiency won't be much better at the same process node. You can just pump more power through each ASIC die) Edit - I misread your comment. ASIC designers will use FPGAs to test their design but it won't be optimized for FPGAs which have a different logic-and-memory characteristic than ASICs. There aren't many great SHA256 FPGA implementations, largely because there's not that much demand for one
- the8472 1y ago
  > but ASICs properly take on negative value when they're no longer profitable to mine with No matmul coin where the hardware could be repurposed for AI stuff?
  - 15155 1y ago
    Modern BTC ASICs consist of 1600-3200 SHA256 cores and only output nonces for sha256(sha256(btcBlockHeader)) - there's no memory or ability to obtain other output.
    - throwawaymaths 1y ago
      always thought it might be cool to repurpose fast double sha engines for error detection in storage arrays
  - throwawaymaths 1y ago
    matmul isn't a trapdoor function
Retr0id 1y ago
Unfortunately I think most of that innovation happened behind closed doors, because everyone wanted to maintain their competitive advantages.
- sMarsIntruder 1y ago
  Yes, ASICS are definitely very closed source for that specific reason.
15155 1y ago
Yes, but a designed-for-FPGA SHA256 implementation looks very different than an ASIC SHA256 implementation - the ASIC has far greater routing flexibility and density, and can therefore use far more combinatorial logic between register stages. (ASIC simulation on an FPGA will retain the combinatorial stages but run at dramatically lower fMax)
- benlivengood 1y ago
  I should have been a little clearer. I meant that the miners spent a brief period optimizing FPGAs before they abandoned them entirely for ASICs, but during that brief period I'm guessing they squeezed as many hashes/watt out of the FPGAs as they could.

Yes, hard silicon will be another magnitude more performant than FPGAs and GPUs, but ASICs properly take on negative value when they're no longer profitable to mine with. (Note that efficiency won't be much better at the same process node. You can just pump more power through each ASIC die) Edit - I misread your comment. ASIC designers will use FPGAs to test their design but it won't be optimized for FPGAs which have a different logic-and-memory characteristic than ASICs. There aren't many great SHA256 FPGA implementations, largely because there's not that much demand for one

the8472 1y ago
> but ASICs properly take on negative value when they're no longer profitable to mine with No matmul coin where the hardware could be repurposed for AI stuff?
- 15155 1y ago
  Modern BTC ASICs consist of 1600-3200 SHA256 cores and only output nonces for sha256(sha256(btcBlockHeader)) - there's no memory or ability to obtain other output.
  - throwawaymaths 1y ago
    always thought it might be cool to repurpose fast double sha engines for error detection in storage arrays
- throwawaymaths 1y ago
  matmul isn't a trapdoor function

Retr0id 1y ago

Unfortunately I think most of that innovation happened behind closed doors, because everyone wanted to maintain their competitive advantages.

sMarsIntruder 1y ago
Yes, ASICS are definitely very closed source for that specific reason.

15155 1y ago

Yes, but a designed-for-FPGA SHA256 implementation looks very different than an ASIC SHA256 implementation - the ASIC has far greater routing flexibility and density, and can therefore use far more combinatorial logic between register stages. (ASIC simulation on an FPGA will retain the combinatorial stages but run at dramatically lower fMax)

benlivengood 1y ago
I should have been a little clearer. I meant that the miners spent a brief period optimizing FPGAs before they abandoned them entirely for ASICs, but during that brief period I'm guessing they squeezed as many hashes/watt out of the FPGAs as they could.