3 ms·Now try a fully unrolled/pipelined design that emits one hash per clock cycle for actual parallelization.by 15155 1y agoNow try a fully unrolled/pipelined design that emits one hash per clock cycle for actual parallelization.deleted 1y ago[deleted]m3kw9 1y agoOr try hardcoding a few billion trillions of premade hashesnayuki 1y agohttps://en.wikipedia.org/wiki/Rainbow_table https://en.wikipedia.org/wiki/Rainbow_table ?m3kw9 1y agoIt would be called galaxy tablepicture 1y agoI know why you're downvoted, but it's true, the author is not using FPGAs correctly.