4 ms·
from a strict ML perspective, stacking, chiplets, multi-reticle are not going to help. that is, ML is about periodic shrinks producing squared improvements to
by markhahn 1y ago
from a strict ML perspective, stacking, chiplets, multi-reticle are not going to help.
that is, ML is about periodic shrinks producing squared improvements to device density at iso-area, and thus costs. if you have to change equipment, ML (in this narrow sense) is out the window. if you have to spend linear resources to stack die or chiplets, that's also not ML-compatible (because linear, not 1/(shrink^2))
vertical flash is interesting because it appears to scale surprisingly well - that is, extra layers don't seem to exponentially degrade yield. I'm not sure any of that applies to logic, though.
- kurthr 1y agoYep, only yield improvements and equipment depreciation are really in the cards. Cost per transistor increased from 7nm to 5nm, but we're about at breakeven with 3nm again. If there's not real fab competition at 2nm then prices per transistor likely won't fall. I suspect the same is true at 1nm. It doesn't feel like any of the alternatives (CNT etc) are really able to step up right now either. https://www.chipstrat.com/p/what-happens-if-tsmc-controls-it https://www.chipstrat.com/p/what-happens-if-tsmc-controls-it My feeling is that algorithmic improvements to LLMs may continue for another order of magnitude or two though. That could continue the scaling for a while. Of course fixed development costs are now over $1B at 2nm, so if you're not making a large number of die (>1M at $1k/ea), it makes no sense to scale.