I'm contemplating about building 32-bit CPU from 74AUC family (fastest CMOS logic available, second only to ECL parts) and register file in asynchronous SRAM. I

I'm contemplating about building 32-bit CPU from 74AUC family (fastest CMOS logic available, second only to ECL parts) and register file in asynchronous SRAM. I think the trouble with FPGA implementation is that some tricks I want to use doesn't translate well, like tri-state bus muxing or FET switches on some paths to reduce propagation delays.