3 ms·

More parallelism. Less clock. More l1 cache per CPU and less disk stalls. Are there plenty of tricks in the sea, when clockspeed goes flat? Dual ported TCAM me

More parallelism. Less clock. More l1 cache per CPU and less disk stalls. Are there plenty of tricks in the sea, when clockspeed goes flat? Dual ported TCAM memory isn't getting faster and we've got to 1,000,000 prefixes in the internet and ipv6 are 4 times bigger. Memory speed is a real issue.

SlowTao 1y ago
The question is at what cost? Cache hasnt scaled down for a long while now, it is part of why it takes up so much die space nowadays. Dont mistake technical viability for economic viability.
- phkahler 1y ago
  I'm wondering if cache is due for a one time doubling of line length. Apple did it, but they seem to be unique in that.
  - ggm-at-algebras 1y ago
    I think its possible. When 128 bits came along, I wondered if the very long instruction word people were going to come back into the room. If we imagine mapping addressing into the world, how about making some rules about top bits addressing other nodes in the DC and see how "shared memory" works between distinct racks?
- ggm-at-algebras 1y ago
  What does economics in die area say about using die for highly repeatable simple memory forms, vs complex instruction/ALU? I would think there is a balance point between more cores, and faster cores with more cache and more lanes between them. We're on 8 as a mixture of fast and slow, hot and cool, on almost all personal devices now. I routinely buy Intel instruction racks with 16 per CPU construct, and a TB of memory. At one remove, chips seem to be fulfilling my mission but I am not in GPU/TPU land. Although I note, FPGA/GPU/TPU seems like where a lot of the mental energy goes these days. VLSI is a black art. Quantum effects are close enough to magic I feel confident saying few people today understand VLSI. I know I don't, I barely understand virtual memory. I ache for the days when a zero pointer was a valid address on a pdp11
eru 1y ago
Moore's law isn't about clockspeed.
- ggm-at-algebras 1y ago
  There has been a relationship between die area and speed for much of time. That stopped being true. Perhaps it was only a side effect of shorter paths on chip.
  - eru 1y ago
    You might be talking about https://en.wikipedia.org/wiki/Dennard_scaling https://en.wikipedia.org/wiki/Dennard_scaling

SlowTao 1y ago

The question is at what cost? Cache hasnt scaled down for a long while now, it is part of why it takes up so much die space nowadays. Dont mistake technical viability for economic viability.

phkahler 1y ago
I'm wondering if cache is due for a one time doubling of line length. Apple did it, but they seem to be unique in that.
- ggm-at-algebras 1y ago
  I think its possible. When 128 bits came along, I wondered if the very long instruction word people were going to come back into the room. If we imagine mapping addressing into the world, how about making some rules about top bits addressing other nodes in the DC and see how "shared memory" works between distinct racks?
ggm-at-algebras 1y ago
What does economics in die area say about using die for highly repeatable simple memory forms, vs complex instruction/ALU? I would think there is a balance point between more cores, and faster cores with more cache and more lanes between them. We're on 8 as a mixture of fast and slow, hot and cool, on almost all personal devices now. I routinely buy Intel instruction racks with 16 per CPU construct, and a TB of memory. At one remove, chips seem to be fulfilling my mission but I am not in GPU/TPU land. Although I note, FPGA/GPU/TPU seems like where a lot of the mental energy goes these days. VLSI is a black art. Quantum effects are close enough to magic I feel confident saying few people today understand VLSI. I know I don't, I barely understand virtual memory. I ache for the days when a zero pointer was a valid address on a pdp11

eru 1y ago

Moore's law isn't about clockspeed.

ggm-at-algebras 1y ago
There has been a relationship between die area and speed for much of time. That stopped being true. Perhaps it was only a side effect of shorter paths on chip.
- eru 1y ago
  You might be talking about https://en.wikipedia.org/wiki/Dennard_scaling https://en.wikipedia.org/wiki/Dennard_scaling