As far as I know, the memory controller IP on the die, as in the part actually interacting with DDR3 channels, didn't change much over that time. And not inclu

As far as I know, the memory controller IP on the die, as in the part actually interacting with DDR3 channels, didn't change much over that time. And not including support for bigger ranks probably saved some amount of circuitry or allowed higher speed, just like moving permission checks to happen last before writeback in the CPU core :|