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From my understanding consumer sandy bridge<->broadwell line was "cursed" when it came to memory controller in general, including flat out not supporting DDR3 s
by p_l 1y ago
From my understanding consumer sandy bridge<->broadwell line was "cursed" when it came to memory controller in general, including flat out not supporting DDR3 spec in full (multiple versions being physically incapable of generating control signals for certain standard-compliant DDR3 modules)
- snvzz 1y agoThat sounds pretty bad, as it's 4.5 generations (sandy/ivy bridge, haswell+refresh and broadwell). Fortunately, it doesn't matter anymore; Moved that 7900gre to my new machine (Ryzen 9800x3d + 2x 48G DDR5 w/ECC).
- p_l 1y agoAs far as I know, the memory controller IP on the die, as in the part actually interacting with DDR3 channels, didn't change much over that time. And not including support for bigger ranks probably saved some amount of circuitry or allowed higher speed, just like moving permission checks to happen last before writeback in the CPU core :|