> modern FPGA tools have functionality HLS is not good, so I don't know what you are referring to as "modern." I am primarily experienced with large UltraScale

> modern FPGA tools have functionality HLS is not good, so I don't know what you are referring to as "modern." I am primarily experienced with large UltraScale+ and Versal chips - nothing has changed in 15 years here. > basically the same as for an ASIC What does this even mean, specifically? Use RTL examples. ASIC memory access isn't "easy," either (though it is basically the "same.") > partial reconfiguration involves swapping out accelerators for specific functions Tell me you've never used PR without telling me. Current vendor implementations of this are terrible (with Xilinx leading the pack.)