3 ms·

The ability to optimize the memory access and memory configuration is sometimes a game changer. And modern FPGA tools have functionality to make mem access quit

The ability to optimize the memory access and memory configuration is sometimes a game changer. And modern FPGA tools have functionality to make mem access quite easy. Not as easy as a MCU/CPU, but basically the same as for an ASIC. I would also question the premise that mem access is less tedious, easy for MCUs/CPU. Esp if you need determinstic performance and response times. Most CPUs have memory hierarchies. The more practial attempts at dynamic, partial reconfiguration involves swapping out accelerators for specific functions. Encoders, fecoders for different wireless standards, Different curves in crypto for example. And yes somebody has to implement those.

15155 1y ago
> modern FPGA tools have functionality HLS is not good, so I don't know what you are referring to as "modern." I am primarily experienced with large UltraScale+ and Versal chips - nothing has changed in 15 years here. > basically the same as for an ASIC What does this even mean, specifically? Use RTL examples. ASIC memory access isn't "easy," either (though it is basically the "same.") > partial reconfiguration involves swapping out accelerators for specific functions Tell me you've never used PR without telling me. Current vendor implementations of this are terrible (with Xilinx leading the pack.)