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After years of reverse engineering, work ongoing, https://github.com/openxc7 https://github.com/openxc7 Open source FPGA toolchain for AMD/Xilinx Series 7 ch

After years of reverse engineering, work ongoing, https://github.com/openxc7 https://github.com/openxc7 Open source FPGA toolchain for AMD/Xilinx Series 7 chips, including Kintex-7. Supports Kintex7 (including 325/420/480t), Artix7, Spartan7 and Zynq7 https://f4pga.org https://f4pga.org & https://news.ycombinator.com/item?id=32861075 https://news.ycombinator.com/item?id=32861075 (umbrella project) Open source toolchain for the development of FPGAs of multiple vendors. Currently, it targets the Xilinx 7-Series, Lattice iCE40, Lattice ECP5 FPGAs, QuickLogic EOS S3 and is gradually being expanded to provide a comprehensive end-to-end FPGA synthesis flow. https://www.bunniestudios.com/blog/2017/litex-vs-vivado-first-impressions/ https://www.bunniestudios.com/blog/2017/litex-vs-vivado-firs... > There’s already IP cores for DRAM, PCI express, ethernet, video, a softcore CPU (your choice of or1k or lm32) and more.. LiteX produces a design that uses about 20% of an XC7A50 FPGA with a runtime of about 10 minutes, whereas Vivado produces a design that consumes 85% of the same FPGA with a runtime of about 30-45 minutes. https://news.ycombinator.com/item?id=39836745#39922534 https://news.ycombinator.com/item?id=39836745#39922534 > you can.. get [FPGA] parts for significant discounts in 1-off quantities through legit Chinese distributors like LCSC. For example, a XC7A35T-2FGG484I is 90$ on Digikey and 20$ at LCSC. I think a personalized deal for that part would be cheaper than 20$ though...

anon-3988 1y ago
Do you think its possible for someone to enter the industry through this open source solution? I have always wanted to play around with FPGAs but have no idea where to even begin.
- transpute 1y ago
  Some contributors to the open hardware community (https://fossi-foundation.org/events/archive https://fossi-foundation.org/events/archive) can be followed on social media. See videos from FOSSI conferences and comments in these HN threads: 2023, "FPGA Dev Boards for $150 or Less", 80 comments, https://news.ycombinator.com/item?id=38161215 https://news.ycombinator.com/item?id=38161215 2021, "FPGA dev board that's cheap, simple and supported by OSS toolchain", 70 comments, https://news.ycombinator.com/item?id=25720531 https://news.ycombinator.com/item?id=25720531 Not an FPGA, but if you already have a recent Ryzen device, the AMD NPU might be worth a look, with Xilinx lineage and current AI/LLM market frenzy, https://news.ycombinator.com/item?id=43671940 https://news.ycombinator.com/item?id=43671940 > The Versal AI Engine is the NPU. And the Ryzen CPUs NPU is almost exactly a Versal AI Engine IP block to the point that in the Linux kernel they share the same driver (amdxdna) and the reference material the kernel docs link to for the Ryzen NPUs is the Versal SoC's AI Engine architecture reference manual. At one point, cheap ex-miner FPGAs were on eBay, https://hackaday.com/2020/12/10/a-xilinx-zynq-linux-fpga-board-for-under-20-the-windfall-of-decommissioned-crypto-mining/ https://hackaday.com/2020/12/10/a-xilinx-zynq-linux-fpga-boa.... The Zynq (Arm + Xilinx FPGA) dev board is around $200, https://www.avnet.com/americas/products/avnet-boards/avnet-board-families/zuboard-1cg/ https://www.avnet.com/americas/products/avnet-boards/avnet-b.... There was an M.2 Xilinx FPGA (PicoEVB) that conveniently fit into a laptop for portable development, but it's not sold anymore. PCIe FPGAs are used for DMA security testing, some of those boards are available, https://github.com/ufrisk/pcileech-fpga https://github.com/ufrisk/pcileech-fpga
- skhameneh 1y ago
  Maybe try https://icestudio.io/ https://icestudio.io/
- burnt-resistor 1y ago
  Need fundamentals of combinational and sequential logic, followed by perhaps a course on hardware/software interfacing to grok timing parameters like setup and hold time, propagation delay, fan in, fan out. FPGAs can be developed using CAE-like systems or SystemVerilog, VHDL, or something modern like Veryl. Real FPGAs include acceleration blocks like DRAM, SRAM, CAM, shifters, ALU elements, and/or ARM cores. At the end of the day though, the best teacher is to learn by doing and finding venues to ask questions.
- whatagreatboy 1y ago
  No. It's not competitive. You'll spend previous time (which should be spent on prototyping an design) on solving bugs and writing infrastructure code. Reverse engineering has not been a viable effort for a long time now.
phendrenad2 1y ago
How well does this actually work on the larger Kintex chips? Are there any projects that show it in action?
- transpute 1y ago
  https://news.ycombinator.com/item?id=39836745#39837900 https://news.ycombinator.com/item?id=39836745#39837900 > There's been some interesting recent work to get the QMTech Kintex7-325 board (among others) supported under yosys/nextpnr.. It works well enough now to build a RISC-V SoC capable of running Linux https://riscv.or.jp/wp-content/uploads/RV-Days_Tokyo_2024_Summer_paper_7.pdf https://riscv.or.jp/wp-content/uploads/RV-Days_Tokyo_2024_Su... 32-bit MMU/No-MMU Linux-capable RISC-V softcore with rich peripherals is implemented by pure Verilog, and supported by OpenXC7, the FOSS FPGA toolchain.. These are still modern devices: 7-Series lifetime extended to 2035. https://github.com/regymm/quasiSoC https://github.com/regymm/quasiSoC
hardolaf 1y ago
You're conflating open source IP cores such as LiteX with open source FPGA tooling to try to make the latter look better by using the former. Everyone knows that vendor IP is pretty terrible if you don't use it in the very narrow window in which it's validated and tested. That's why big defense contractors all use either the Northwest Logic or Rambus PCI-e cores on everything prior to Versal. But at the same time, those cores are big and powerful, and optimize horribly because the customers who actually use them need all of those features. Those customers aren't really concerned with area but rather with meeting performance requirements. Using the Xilinx provided QDMA core, I've been able to achieve line rate performance on PCI-e 4.0 x16 for large DMA transactions with a setup time of about 3 total days of work. I'd like to see an open source solution that could even do that with just ACKing raw TLPs because I haven't found one yet. As for pricing, AMD/Xilinx and Altera don't want you as a customer. They want to sign $10M+/yr accounts or accounts which push the envelope of what's possible in terms of frequency (HFT). And they price their products accordingly for the public. If you actually end up as a direct customer, the prices are significantly cheaper to the point where those cheaper Chinese vendors don't make sense to use.

anon-3988 1y ago

Do you think its possible for someone to enter the industry through this open source solution? I have always wanted to play around with FPGAs but have no idea where to even begin.

transpute 1y ago
Some contributors to the open hardware community (https://fossi-foundation.org/events/archive https://fossi-foundation.org/events/archive) can be followed on social media. See videos from FOSSI conferences and comments in these HN threads: 2023, "FPGA Dev Boards for $150 or Less", 80 comments, https://news.ycombinator.com/item?id=38161215 https://news.ycombinator.com/item?id=38161215 2021, "FPGA dev board that's cheap, simple and supported by OSS toolchain", 70 comments, https://news.ycombinator.com/item?id=25720531 https://news.ycombinator.com/item?id=25720531 Not an FPGA, but if you already have a recent Ryzen device, the AMD NPU might be worth a look, with Xilinx lineage and current AI/LLM market frenzy, https://news.ycombinator.com/item?id=43671940 https://news.ycombinator.com/item?id=43671940 > The Versal AI Engine is the NPU. And the Ryzen CPUs NPU is almost exactly a Versal AI Engine IP block to the point that in the Linux kernel they share the same driver (amdxdna) and the reference material the kernel docs link to for the Ryzen NPUs is the Versal SoC's AI Engine architecture reference manual. At one point, cheap ex-miner FPGAs were on eBay, https://hackaday.com/2020/12/10/a-xilinx-zynq-linux-fpga-board-for-under-20-the-windfall-of-decommissioned-crypto-mining/ https://hackaday.com/2020/12/10/a-xilinx-zynq-linux-fpga-boa.... The Zynq (Arm + Xilinx FPGA) dev board is around $200, https://www.avnet.com/americas/products/avnet-boards/avnet-board-families/zuboard-1cg/ https://www.avnet.com/americas/products/avnet-boards/avnet-b.... There was an M.2 Xilinx FPGA (PicoEVB) that conveniently fit into a laptop for portable development, but it's not sold anymore. PCIe FPGAs are used for DMA security testing, some of those boards are available, https://github.com/ufrisk/pcileech-fpga https://github.com/ufrisk/pcileech-fpga
skhameneh 1y ago
Maybe try https://icestudio.io/ https://icestudio.io/
burnt-resistor 1y ago
Need fundamentals of combinational and sequential logic, followed by perhaps a course on hardware/software interfacing to grok timing parameters like setup and hold time, propagation delay, fan in, fan out. FPGAs can be developed using CAE-like systems or SystemVerilog, VHDL, or something modern like Veryl. Real FPGAs include acceleration blocks like DRAM, SRAM, CAM, shifters, ALU elements, and/or ARM cores. At the end of the day though, the best teacher is to learn by doing and finding venues to ask questions.
whatagreatboy 1y ago
No. It's not competitive. You'll spend previous time (which should be spent on prototyping an design) on solving bugs and writing infrastructure code. Reverse engineering has not been a viable effort for a long time now.

phendrenad2 1y ago

How well does this actually work on the larger Kintex chips? Are there any projects that show it in action?

transpute 1y ago
https://news.ycombinator.com/item?id=39836745#39837900 https://news.ycombinator.com/item?id=39836745#39837900 > There's been some interesting recent work to get the QMTech Kintex7-325 board (among others) supported under yosys/nextpnr.. It works well enough now to build a RISC-V SoC capable of running Linux https://riscv.or.jp/wp-content/uploads/RV-Days_Tokyo_2024_Summer_paper_7.pdf https://riscv.or.jp/wp-content/uploads/RV-Days_Tokyo_2024_Su... 32-bit MMU/No-MMU Linux-capable RISC-V softcore with rich peripherals is implemented by pure Verilog, and supported by OpenXC7, the FOSS FPGA toolchain.. These are still modern devices: 7-Series lifetime extended to 2035. https://github.com/regymm/quasiSoC https://github.com/regymm/quasiSoC

hardolaf 1y ago

You're conflating open source IP cores such as LiteX with open source FPGA tooling to try to make the latter look better by using the former. Everyone knows that vendor IP is pretty terrible if you don't use it in the very narrow window in which it's validated and tested. That's why big defense contractors all use either the Northwest Logic or Rambus PCI-e cores on everything prior to Versal. But at the same time, those cores are big and powerful, and optimize horribly because the customers who actually use them need all of those features. Those customers aren't really concerned with area but rather with meeting performance requirements. Using the Xilinx provided QDMA core, I've been able to achieve line rate performance on PCI-e 4.0 x16 for large DMA transactions with a setup time of about 3 total days of work. I'd like to see an open source solution that could even do that with just ACKing raw TLPs because I haven't found one yet. As for pricing, AMD/Xilinx and Altera don't want you as a customer. They want to sign $10M+/yr accounts or accounts which push the envelope of what's possible in terms of frequency (HFT). And they price their products accordingly for the public. If you actually end up as a direct customer, the prices are significantly cheaper to the point where those cheaper Chinese vendors don't make sense to use.