That is not enough. The generated Verilog code can be very opaque which makes it very difficult to analyze in cycle-accurate simulators. It also is (afaik) most

That is not enough. The generated Verilog code can be very opaque which makes it very difficult to analyze in cycle-accurate simulators. It also is (afaik) mostly impossible to automatically correlate an error in the Verilog code with a specific line in the Chisel code. Also pure Verilog is often not enough. You also need tons of vendor-specific pragmas to ensure that the design synthesizes well.