5 ms·

One important detail the article omits: it is possible for the software running on the Commodore 64 to prevent being "frozen" by this technique. Because the pro

One important detail the article omits: it is possible for the software running on the Commodore 64 to prevent being "frozen" by this technique. Because the processor needs the NMI interrupt to run the freeze routine, the software can pre-empt it by pulling down the NMI line on its own. This can be done using the second CIA I/O chip, whose interrupt output pin is connected to the NMI line. By making the CIA chip generate the NMI and never acknowledging it, the software will ensure that the NMI line is always pulled low and the freezer will not work.

WJW 1y ago
That's a clever trick, but giving up all the useful types of NMIs seems like a steep price to pay.
- michalpleban 1y ago
  Commodore 64 software hardly ever uses the NMI interrupt, because there is also the maskable IRQ interrupt which can be generated by the first CIA chip, and also, unlike NMI, by the video chip VIC for the raster interrupt. It is also much more useful because it is maskable - the software can temporarily turn it off when it is not desirable to be interrupted. The only thing the NMI can do that IRQ cannot is detecting that the Restore key was pressed, but that is seldom useful.
- bombcar 1y ago
  It would be useful during boss segments perhaps, as an extra challenge.
fernirello 1y ago
Clarification question, having read OP yet having missed some fine details: I presume you mean that software could set some CIA-II register to keep the NMI line to the CPU down indefinitely. Since what triggers the handling of an NMI is the transition from high to low, that means no other handler (in particular the Freeze Frame's) would get executed. And one'd also need to redirect the NMI vector, which normally is in Kernel ROM, to a dummy handler consisting of an RTI or little more. Correct?
- michalpleban 1y ago
  Yes, that's absolutely correct
  - fernirello 1y ago
    Thank you!
    - michalpleban 1y ago
      An addendum: the way you would program the CIA registers to pull the NMI low would most likely be to set up one of its timers on a very short count period (IIRC four system clock cycles is the lowest the chip can do) and make it generate the underflow interrupt. The chip holds the interrupt line low until you acknowledge the interrupt by reading the interrupt source register. If you never get to read it, the interrupt line stays low forever.

WJW 1y ago

That's a clever trick, but giving up all the useful types of NMIs seems like a steep price to pay.

michalpleban 1y ago
Commodore 64 software hardly ever uses the NMI interrupt, because there is also the maskable IRQ interrupt which can be generated by the first CIA chip, and also, unlike NMI, by the video chip VIC for the raster interrupt. It is also much more useful because it is maskable - the software can temporarily turn it off when it is not desirable to be interrupted. The only thing the NMI can do that IRQ cannot is detecting that the Restore key was pressed, but that is seldom useful.
bombcar 1y ago
It would be useful during boss segments perhaps, as an extra challenge.

fernirello 1y ago

Clarification question, having read OP yet having missed some fine details: I presume you mean that software could set some CIA-II register to keep the NMI line to the CPU down indefinitely. Since what triggers the handling of an NMI is the transition from high to low, that means no other handler (in particular the Freeze Frame's) would get executed. And one'd also need to redirect the NMI vector, which normally is in Kernel ROM, to a dummy handler consisting of an RTI or little more. Correct?

michalpleban 1y ago
Yes, that's absolutely correct
- fernirello 1y ago
  Thank you!
  - michalpleban 1y ago
    An addendum: the way you would program the CIA registers to pull the NMI low would most likely be to set up one of its timers on a very short count period (IIRC four system clock cycles is the lowest the chip can do) and make it generate the underflow interrupt. The chip holds the interrupt line low until you acknowledge the interrupt by reading the interrupt source register. If you never get to read it, the interrupt line stays low forever.