I don't have the bandwidth to generate graphics (and this is necessarily very application-specific), but here's the general gist: A PCB stackup has multiple la

I don't have the bandwidth to generate graphics (and this is necessarily very application-specific), but here's the general gist: A PCB stackup has multiple layers of metal with dielectric material sandwiched between them. In a 6+-layer PCB, it might be reasonable to have multiple power and ground planes (sheets of copper) at a close spacing. If you refer back to your electronic component geometries, we can see this as a parallel-plate capacitor. Say your plane spacing is 0.2mm (2x10e-4 m) and your dielectric constant is ~4. That would make the planes a capacitor with value ~1.6x10e-14F/mm^2 or ~0.16 pF/mm^2. That may not seem like much, but it means the capacitance under a 1cm^2 chip is 16pF, and the impedance at 100 MHz is ~100Ω. Because the chip can then have very short (sub-mm) vias as its entire trace to power, the inductance is also very low. This is a good resource for a deeper dive: https://docs.amd.com/r/en-US/ug583-ultrascale-pcb-design/Plane-Inductance https://docs.amd.com/r/en-US/ug583-ultrascale-pcb-design/Pla...