You're right that it's the IO (buses and memory) that the main limit. The problem is that a design around a central CPU doesn't scale, there's not enough IO, no

You're right that it's the IO (buses and memory) that the main limit. The problem is that a design around a central CPU doesn't scale, there's not enough IO, not enough pins, if you want to DMA packets from 24 interfaces onto main memory and have different cores operate on it is just infeasible with current designs.